Numerals presented herebelow in square brackets—[ ]—are keyed to the list of references found towards the close of the present disclosure.
Initial reference is made to prior art in FIGS. 1(a), (b) and (c). It is generally known that the leakage power consumption of VLSI logic and memories increases rapidly with CMOS technology scaling. One way to reduce the power is to cut off the power line in standby mode when the circuit is not operating [1]. However, such a power gating structure (FIG. 1(a)) is not widely used in latches and other memory elements since the stored data information is completely lost when the power switch is off, and data recovery process significantly degrades system performance [3]. To solve this problem, a diode (FIG. 1(b)) or a transistor (FIG. 1(c)) can be put in parallel with the power gating device to serve as a clamping device for the virtual supply/ground rail, thus maintaining adequate voltage across the memory elements for state retention in standby mode. However, this extra clamping device increases the area and capacitance of the power gating structure, thereby degrading performance, power and leakage.
Reference is also made to prior art in FIG. 2 where a double gating arrangement comprising two gates is used in AGC (Automatic Gain Control) circuit [2]. In this prior art arrangement, both gates are on the same side of the silicon conducting channel in a conventional planar CMOS device structure. The two gates are in series with the first gate performing the AGC function while the second gate receives the input high frequency signals to be amplified. Both gates function simultaneously such that the high frequency input signal is amplified with a controllable and variable gain.
Double-gate (DG) technology is emerging as a potential candidate beyond 45 nm node technologies due to its distinct advantages for scaling to very short-channel lengths [4]. Furthermore, DG devices offer the unique opportunities for operating two (tied) gates simultaneously or independently controlling each gate [5]. For an independently controlled symmetrical DG device, each gate is decoupled and independently accessed/biased, and a single DG device acts as two parallel transistors [5]. Generally, an evolving need has been recognized in connection with effectively employing DG technology to help overcome the shortcomings and disadvantages of prior efforts as just described.
In the present invention, a symmetrical double-gate device is configured in a double-gating arrangement to provide improved data retention capability in power-gating structure. There are several distinctions from the AGC double-gating prior art in terms of device structures, configurations, operations, and intended use. For device structure, the two gates are on opposite sides of the silicon conducting channel in a symmetrical double-gate device structure, while the AGC circuit employs two gates on the same side of the silicon conducting channel in a conventional planar CMOS device structure. The two-gates are configured in “parallel” (as opposed to “series” configuration in AGC prior art), with the first gate configured to perform the power switch function, while the second gate is configured to serve as a clamping diode. When the power switch (first gate) is “On”, the clamping diode (second gate) is bypassed (or disabled), thus maintaining the circuit performance. When the power switch is “Off”, the clamping diode kicks in (becomes functional) to clamp the virtual power supply rail, thus improving the data retention capability of data storage elements while containing the leakage. As such, the two gates provide the desired functions in a complementary manner (not “simultaneously”). On the other hand, in the AGC double-gating prior art, both gates have to be “On” simultaneously to perform the desired function.